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HS4318ESS01H bảng dữ liệu(PDF) 63 Page - Renesas Technology Corp |
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HS4318ESS01H bảng dữ liệu(HTML) 63 Page - Renesas Technology Corp |
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63 / 68 page ![]() HD404318 Series 61 Serial Interface Timing Characteristics (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, Ta = –20 to +75 °C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1— — t cyc Load shown in figure 56 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 56 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 56 1 Transmit clock rise time t SCKr SCK — — 80 ns Load shown in figure 56 1 Transmit clock fall time t SCKf SCK — — 80 ns Load shown in figure 56 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 56 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1— — t cyc 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc 1 Transmit clock rise time t SCKr SCK — — 80 ns 1 Transmit clock fall time t SCKf SCK — — 80 ns 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 56 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 Note: 1. Refer to figure 55. tCPr tCPf VCC – 0.5 V 0.5 V OSC1 tCPH tCPL 1/fCP Figure 51 External Clock Timing |
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