M38263EBFS datasheet(50/91 Pages) RENESAS

50 / 91 page

Rev.1.00

Sep 06, 2006

page 50 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Watchdog Timer

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software runaway).

The watchdog timer consists of an 8-bit watchdog timer L and a 6-

bit watchdog timer H. At reset or writing to the watchdog timer

control register (address 003716), the watchdog timer is set to

“3FFF16”. When any data is not written to the watchdog timer con-

trol register (address 003716) after reset, the watchdog timer is

stopped. The watchdog timer starts to count down from “3FFF16”

by writing to the watchdog timer control register and an internal re-

set occurs at an underflow. Accordingly, when using the watchdog

timer function, write the watchdog timer control register before an

underflow. The watchdog timer does not function when writing to

the watchdog timer control register has not been done after reset.

When not using the watchdog timer, do not write to it. When the

watchdog timer control register is read, the following values are

read:

● value of high-order 6-bit counter

● value of STP instruction disable bit

● value of count source selection bit.

When the STP instruction disable bit is “0”, the STP instruction is

enabled. The STP instruction is disabled when this bit is set to “1”.

If the STP instruction which is disabled is executed, it is processed

as an undefined instruction, so that a reset occurs internally.

This bit can be set to “1” but cannot be set to “0” by program. This

bit is “0” after reset.

When the watchdog timer H count source selection bit is “0”, the

detection time is set to 8.19 s at f(XCIN) = 32 kHz and 32.768 ms

at f(XIN) = 8 MHz.

When the watchdog timer H count source selection bit is “0”, the

detection time is set to 32 ms at f(XCIN) = 32 kHz and 128 µs at

f(XIN) = 8 MHz. There is no difference in the detection time be-

tween the middle-speed mode and the high-speed mode.

Fig. 52 Block diagram of watchdog timer

Fig. 53 Structure of watchdog timer control register

Fig. 54 Timing of reset output

XIN

Data bus

XCIN

“1”

“0”

Internal

system clock

selection bit

(Note)

“0”

“1”

1/16

Watchdog timer H count

source selection bit

Reset circuit

Undefined instruction

Reset

“3F16” is set when

watchdog timer is

written to.

Internal reset

RESET

Reset release time wait

“FF16” is set when

watchdog timer is

written to.

STP instruction

STP instruction disable bit

Watchdog timer

H (6)

Watchdog timer

L (8)

Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode.

Watchdog timer register

(WDTCON: address 003716)

STP instruction disable bit

0 : STP instruction enabled

1 : STP instruction disabled

Watchdog timer H count source selecion bit

0 : Watchdog timer L underflow

1 : f(XIN)/16 or f(XCIN)/16

Watchdog timer H (for read-out of high-order 6 bit)

“3FFF16” is set to the watchdog timer by writing values to this address.

Internal

reset signal

Watchdog timer

detection

Approx. 1 ms (f(XIN) = 8 MHZ)

f(XIN)

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