M38261EBFS datasheet(80/91 Pages) RENESAS

80 / 91 page

Rev.1.00

Sep 06, 2006

page 80 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

(5)

Pin state after transmit completion

The TxD pin holds the state of the last bit of the transmission after transmission completion. When

the internal clock is selected for the transmit clock in the clock synchronous serial I/O mode, the

SCLK1 pin holds “H”.

(6)

Serial I/O1 enable bit during transmit operation

When the serial I/O1 enable bit (bit 7 of serial I/O1 control register) is set to “0” (serial I/O1

disabled) when data transmission is in progress, the transmission progress internally. However,

the external data transfer is terminated because the pins become regular I/O ports. In addition to

this, when data is written to the transmission buffer register, data transmission is started internally.

When the serial I/O1 enable bit is set to “1”, the transmission is output to the TxD pin in the middle

of the transfer.

(7)

Transmission control when external clock is selected

When an external clock is used as the synchronous clock for data transmission, set the transmit

enable bit to “1” at “H” of the SCLK1 input level. Also, write the transmit data to the transmit buffer

(8)

Receive operation in clock synchronous serial I/O mode

When receiving data in the clock synchronous serial I/O mode, set not only the receive enable bit

but also the transmit enable bit to “1”. Then write dummy data to the transmission buffer register.

When the internal clock is selected as the synchronous clock, the synchronous clock is output at

this point and the receive operation is started. When the external clock is selected as the transfer

clock, the serial I/O becomes ready for data receive at this point and, when the external clock is

input to the clock input pin, the receive operation is started. The P45/TxD pin outputs the dummy

data written in the transmission buffer register.

(9)

Transmit and receive operation in clock synchronous serial I/O mode

When stopping transmitting and receiving operations in the clock synchronous serial I/O mode, set

the receive enable bit and the transmit enable bit to “0” simultaneously. If only one of them is

stopped the receive or transmit operation may loose synchronization, causing a bit slippage.

3.3.7 Notes on serial I/O2

(1)

Switching synchronous clock

When switching the synchronous clock by the serial I/O2 synchronous clock selection bit (bit 6 of

serial I/O2 control register (address 1D16)), initialize the serial I/O2 counter (write data to serial I/

O2 register (address 1F16)).

(2)

Notes when selecting external clock

When an external clock is selected as the synchronous clock, the SOUT2 pin holds the output level

of D7 after transmission is completed. However, if the clock is input to the serial I/O continuously,

the serial I/O2 register continue the shift operation and output data from the SOUT2 pin continuously.

A write operation to the serial I/O2 register must be performed when the SCLK21 pin is “H”.

When the internal clock is selected as the synchronous clock, the SOUT2 pin holds the high-

impedance state after transmission.

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