M3826AE2FS datasheet(66/91 Pages) RENESAS

66 / 91 page

Rev.1.00

Sep 06, 2006

page 66 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

TIMING REQUIREMENTS

Table 24 Timing requirements 1

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

125

250

105

800

370

220

100

1000

400

200

Note: When bit 6 of address 001A16 is “1”.

Divide this value by four when bit 6 of address 001A16 is “0”.

Reset input “L” pulse width

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT2 input “H” pulse width

INT0 to INT2 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

Serial I/O1 input hold time

Serial I/O2 clock input cycle time (Note)

Serial I/O2 clock input “H” pulse width (Note)

Serial I/O2 clock input “L” pulse width (Note)

Serial I/O2 input set up time

Serial I/O2 input hold time

tw(RESET)

tc(XIN)

twH(XIN)

twL(XIN)

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

tsu(RXD–SCLK1)

th(SCLK1–RXD)

tc(SCLK2)

twH(SCLK2)

twL(SCLK2)

tsu(SIN2–SCLK2)

th(SCLK2–SIN2)

Symbol

Parameter

Limits

Min.

µs

Unit

Typ.

Max.

Table 25 Timing requirements 2

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

125

500/(VCC-2)

250/(VCC-2)–20

230

2000

950