MSC8113 datasheet(26/44 Pages) FREESCALE

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MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freescale Semiconductor

2.5.6

DSI Timing

The timings in the following sections are based on a 20 pF capacitive load.

2.5.6.1

DSI Asynchronous Mode

Figure 12. DMA Signals

Table 18. DSI Asynchronous Mode Timing

No.

Characteristics

Min

Max

Unit

100

Attributes1 set-up time before strobe (HWBS[n]) assertion

1.5

—

101

Attributes1 hold time after data strobe deassertion

1.3

—

102

Read/Write data strobe deassertion width:

•

DCR[HTAAD] = 1

— Consecutive access to the same DSI

— Different device with DCR[HTADT] = 01

— Different device with DCR[HTADT] = 10

— Different device with DCR[HTADT] = 11

•

DCR[HTAAD] = 0

1.8 + TREFCLK

5 + TREFCLK

5 + (1.5

× TREFCLK)

5 + (2.5

× TREFCLK)

1.8 + TREFCLK

—

103

Read data strobe deassertion to output data high impedance

—

8.5

104

Read data strobe assertion to output data active from high impedance

2.0

—

105

Output data hold time after read data strobe deassertion

2.2

—

106

Read/Write data strobe assertion to HTA active from high impedance

2.2

—

107

Output data valid to HTA assertion

3.2

—

108

Read/Write data strobe assertion to HTA valid2

—7.4

109

Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 0, HTA at end of access released at logic 0)

—6.5

110

Read/Write data strobe deassertion to output HTA deassertion.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1)

—6.5

111

Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1

•

DCR[HTADT] = 01

•

DCR[HTADT] = 10

•

DCR[HTADT] = 11

—

5 + TREFCLK

5 + (1.5

× TREFCLK)

5 + (2.5

× TREFCLK)

112

Read/Write data strobe assertion width

1.8 + TREFCLK

—ns

201

Host data input set-up time before write data strobe deassertion

1.0

—

202

Host data input hold time after write data strobe deassertion

1.7

—

Notes:

Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.

This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.

All values listed in this table are tested or guaranteed by design.

REFCLK

DREQ

DONE

DACK/DONE/DRACK

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