MSC8113 datasheet(25/44 Pages) FREESCALE

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Electrical Characteristics

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

2.5.5.2

CLKIN to CLKOUT Skew

Table 17 describes the CLKOUT-to-CLKIN skew timing.

For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing

values specified for CLKIN synchronization. Figure 11 shows the relationship between the CLKOUT and CLKIN timings.

2.5.5.3

DMA Data Transfers

Table 17 describes the DMA signal timing.

The DREQ

signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ

according to the timings in Table 17. Figure 12 shows synchronous peripheral interaction.

Table 16. CLKOUT Skew

No.

Characteristic

Min1

Max1

Units

Rise-to-rise skew

0.0

0.95

Fall-to-fall skew

–1.5

1.0

CLKOUT phase (1.1 V, 133 MHz)

•

Phase high

•

Phase low

2.2

—

CLKOUT phase (1.1 V, 100 MHz)

•

Phase high

•

Phase low

3.3

—

Notes:

A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

CLKOUT skews are measured using a load of 10 pF.

CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

Figure 11. CLKOUT and CLKIN Signals.

Table 17. DMA Signals

No.

Characteristic

Ref = CLKIN

Units

Min

Max

DREQ set-up time before the 50% level of the falling edge of REFCLK

5.0

—

DREQ hold time after the 50% level of the falling edge of REFCLK

0.5

—

DONE set-up time before the 50% level of the rising edge of REFCLK

5.0

—

DONE hold time after the 50% level of the rising edge of REFCLK

0.5

—

DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

0.5

7.5

CLKIN

CLKOUT

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