ADE3800SXL datasheet(34/138 Pages) STMICROELECTRONICS

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ADE3800

34/138

Table 16: Sync Retiming Registers (Sheet 1 of 2)

Addr

Mode

Bits

Rst

Description

SRT_CSYNC_INV

01E0

R/W

[2]

invert vert sync signal extracted from internal SOG

comparator (sog_vs_inv)

R/W

[1]

invert vert sync extracted from composite sync signal on

HSync pin (csync_vs_inv)

R/W

[0]

invert filtered vert sync (filt_vs_inv)

SRT_CSYNC_THR_L

SRT_CSYNC_THR_U

01E1

01E2

R/W

[7:0]

[3:0]

composite sync vertical sync extractor threshold

(this is the narrowest HSync signal sent +50% as a

safety margin) refer to Figure 7

SRT_VSYNC_SEL

01E3

R/W

[2:0]

filtered vert sync source select

0*: VSYNC pin

1: vsync from composite HSYNC pin

2: vsync from composite SOG[0] comparator

3: vsync from composite SOG[1] comparator

4: vsync from composite SOG[2] comparator

5: vsync from alternate SOG source

6 - 7: Reserved

SRT_VSYNC_THR_L

SRT_VSYNC_THR_U

01E4

01E5

R/W

[7:0]

[3:0]

filtered vert sync delay

SRT_COAST_VS_SEL

01E6

R/W

[3]

coast signal trigger edge

0*: rising edge of selected VSync

1: falling edge of selected VSync

R/W

[2:0]

source selection for coast VSync trigger

0*: VSYNC pin

1: vsync from composite HSYNC pin

2: vsync from composite SOG[0] comparator

3: vsync from composite SOG[1] comparator

4: vsync from composite SOG[2] comparator

5: filtered and delayed vsync (normal)

6: vsync from alternate SOG source

7: Reserved

SRT_COAST_RISE_L

SRT_COAST_RISE_M

SRT_COAST_RISE_U

01E7

01E8

01E9

R/W

[7:0]

rising edge of coast, in XCLKs from vsync trigger

SRT_COAST_FALL_L

SRT_COAST_FALL_M

SRT_COAST_FALL_U

01EA

01EB

01EC

R/W

[7:0]

falling edge of coast, in XCLKs from vsync trigger

SRT_HS_CTRL

01EE

R/W

[4]

Edge of inclk on which to sample horizontal sync:

0*: rising edge

1: falling edge (normal)

R/W

[2:0]

HSync Sample Selection for SMUX

0*: reserved

1: llk_HSync (normal)

2: SOG0

3: SOG1

4: SOG2

5: EXT_SOG

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