 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADE3800SXL bảng dữ liệu(PDF) 32 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ADE3800SXL bảng dữ liệu(HTML) 32 Page - STMicroelectronics |
|
|
32 / 138 page  Register Description by Block ADE3800 32/138 LLK_OFFSET_L LLK_OFFSET_U 080B 080C R/W R/W [7:0] [1:0] 00 00 phase offset [7:0] of adc sample clock. LSB is xclk_period/512 = 72ps. phase offset LLK_PULSE_HIGH_EXT 080D R/W [7] 00 inclk pulse extend enable R/W [2:0] inclk pulse extend value. LSB = 0.3ns (typ) LLK_PHASE_RATE_MIN 080E R/W [7:0] 14 phase rate minimum. Sets the upper frequency limit of the PLL. phase_rate_min = xclk_freq * 128 / max_inclk_freq. LLK_STAT_LINE_NB_L LLK_STAT_LINE_NB_U 080F 0810 R/W R/W [7:0] [7:0] 40 00 number of lines over which statistics are gathered number of lines over which statistics are gathered LLK_STAT_SUM_ABS_MAX_L LLK_STAT_SUM_ABS_MAX_U 0811 0812 R/W R/W [7:0] [7:0] 60 00 limit for sum of absolute errors LLK_STAT_MAX_ABS_MAX 0813 R/W [7:0] 04 limit for absolute error LLK_DEADZONE 0814 R/W [3:0] 02 coarse error deadzone, normal operation = 2. LLK_STATUS 0830 R [4] 00 max absolute error exceeded limit, not sticky R [3] sum of absolute errors exceeded limit, not sticky R [2] pll filter overflow condition, not sticky R [1] coarse error is zero status, not sticky R [0] lock status, not sticky LLK_STATUS_PHASE_RATE_I_ 0 LLK_STATUS_PHASE_RATE_I_ 1 LLK_STATUS_PHASE_RATE_I_ 2 LLK_STATUS_PHASE_RATE_I_ 3 0831 0832 0833 0834 R R/W R/W R/W [7:0] [7:0] [7:0] [5:0] 00 00 00 00 pll phase rate, free running readout.b LLK_STATUS_SUM_ABS_L LLK_STATUS_SUM_ABS_U 0835 0836 R R [7:0] [7:0] 00 00 sum of absolute errors readout LLK_STATUS_MAX_ABS 0837 R [7:0] 00 max absolute error readout LLK_MFACTOR_HW_L LLK_MFACTOR_HW_U 0842 0843 R R [7:0] [7:0] 80 02 mfactor shadow hw readout LLK_TEST 084F R/W [7:0] 00 reserved a. recommended setting for bits [2:0] = 110b b. phase rate period (in picoseconds) is: Example: LLK_STATUS_PHASE_RATE_I_[28:0] = 03335BDF , XTAL = 27 MHz phase rate period = 7.409 ns frequency = 134.97 MHz Table 15: Line Lock PLL Registers (Sheet 2 of 2) Register Name Addr Mode Bits Rst Description haseRate ps () LlkStatusPhaseRate 28…0 [] 2 21 – × XTALperiod ps ( × 128 ------------------------------------------------------------------------------------------------------------------------------------------------------ = |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
