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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADE3800SXL bảng dữ liệu(PDF) 65 Page - STMicroelectronics |
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ADE3800SXL bảng dữ liệu(HTML) 65 Page - STMicroelectronics |
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65 / 138 page  65/138 ADE3800 Register Description by Block PGEN_Y_TOT_L PGEN_Y_TOT_U 0603 0604 R/W R/W [7:0] [3:0] 00 00 screen total vertical size in lines PGEN_B_TOP_BOT 0605 R/W [7] 00 top border enable bit R/W [6:4] top border R G B color enable bits R/W [3] bottom border enable bit R/W [2:0] bottom border R G B color enable bits PGEN_B_LFT_RHT 0606 R/W [7] 00 left border enable bit R/W [6:4] left border R G B color enable bits R/W [3] right border enable bit R/W [2:0] right border R G B color enable bits PGEN_GRID0 0607 R/W [7:0] 00 grid ‘s row 0 0: select P0 (bar pattern) 1: select input signal (from scaler) PGEN_GRID1 0608 R/W [7:0] 00 grid ‘s row 1 PGEN_GRID2 0609 R/W [7:0] 00 grid ‘s row 2 PGEN_GRID3 060A R/W [7:0] 00 grid ‘s row 3 PGEN_GRID4 060B R/W [7:0] 00 grid ‘s row 4 PGEN_GRID5 060C R/W [7:0] 00 grid ‘s row 5 PGEN_GRID6 060D R/W [7:0] 00 grid ‘s row 6 PGEN_GRID7 060E R/W [7:0] 00 grid ‘s row 7 PGEN_GRID_X_L PGEN_GRID_X_U 060F 0610 R/W R/W [7:0] [3:0] 00 00 grid cells width, in pixels PGEN_GRID_Y_L PGEN_GRID_Y_U 0611 0612 R/W R/W [7:0] [3:0] 00 00 grid cells height, in lines PGEN_GRID_X_OFFSET_L PGEN_GRID_X_OFFSET_U 0613 0614 R/W R/W [7:0] [3:0] 00 00 grid’s horizontal offset, in pixels PGEN_GRID_Y_OFFSET_L PGEN_GRID_Y_OFFSET_U 0615 0616 R/W R/W [7:0] [3:0] 00 00 grid’s vertical offset, in lines PGEN_P0_MODE 0617 R/W [7:5] 00 number of bars in C0 (actual number -1) R/W [4:2] number of bars in C1 (actual number -1) R/W [1] cell reset enable R/W [0] video replaces C0 enable PGEN_P0_COLOR_B_C0 0618 R/W [7:0] 00 color C0 – blue PGEN_P0_COLOR_G_C0 0619 R/W [7:0] 00 color C0 – green PGEN_P0_COLOR_R_C0 061A R/W [7:0] 00 color C0 – red PGEN_P0_COLOR_B_C1 061B R/W [7:0] 00 color C1 – blue PGEN_P0_COLOR_G_C1 061C R/W [7:0] 00 color C1 – green Table 25: Pattern Generator Registers (Sheet 2 of 3) Register Name Addr Mode Bits Rst Description |
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