ADE3800XT datasheet(29/138 Pages) STMICROELECTRONICS

29 / 138 page

29/138

ADE3800

4.4

Analog Dithering (ADTH)

The ADTH block generates a 3-bit dither pattern ADTH_OUT[2:0] to tune the 10-bit resolution of the

ADC block.

Note:

ADTH_OUT[2:0] is not a register but the generated 3-bit dither output of the ADTH block.

4.4.1

Function

The ADTH block consists of a 32x32x3 bit look up table (LUT). It represents one dither matrix, which

can be read using a programmable addressing technique as well as a programmable output

amplitude control. When ADTH_MAT_CTRL[0] is zero or during the clamp pulse ADTH_OUT[2:0] =

3. During vertical blanking ADTH_OUT[2:0] is set to ADTH_TEST_DITHER[2:0] to provide a

feedback mechanism for calibration.

4.4.2

Addressing Technique

The ADTH block offers a programmable addressing technique to generate various temporal dither

patterns. ADTH_FRAME_CTRL [7:4] is a 4-bit increment value, which defines the horizontal/vertical

displacement of the dither matrix from frame to frame (precisely at rising edge of CLAMP_IN and at

falling edge of VENAB).

After (ADTH_FRAME_CTRL [3:0] + 1) number of frames the horizontal/vertical displacement position

will be reset to zero/zero, only when ADTH_FRAME_CTRL [3:0]> 0.

Note:

To set the frame accumulator to zero, program ADTH_FRAME_CTRL [7:4] to zero and program

ADTH_FRAME_CTRL [3:0]

to 1. ADTH_FRAME_CTRL [7:4] can be independently activated in the

horizontal and vertical dimensions using ADTH_MAT_CTRL [2] and ADTH_MAT_CTRL [3],

respectively.

4.4.3

Output Amplitude Control

The 3-bit LUT output value can be scaled to a reduced dither amplitude using ADTH_MAT_CTRL

[5:4]. After adding the ADTH_MAT_CTRL [7:6] to the (reduced) dither amplitude the final 3-bit

amplitude is output as ADTH_OUT[2:0].

4.4.4

Miscellaneous

During the ADC clamp pulse, the output of the ADTH block is muted; that is the output value is set

to 3 (ADTH_OUT[2:0] = 3). In addition, ADTH_CLAMP_CTRL[7:4] delays the clamp pulse by 0 to

15 clock cycles while muting, and ADTH_CLAMP_CTRL[3:0] adds 0 to 15 clock cycles of muting

after the falling edge of the clamp pulse.

For AFE dither calibration, ADTH_OUT[2:0] can be programmed via ADTH_TEST_DITHER to a

static value during vertical blanking.

ADE3800XT bảng dữ liệu(PDF) 29 Page - STMicroelectronics

ADE3800XT bảng dữ liệu(HTML) 29 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL