ADE3800XT datasheet(56/138 Pages) STMICROELECTRONICS

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ADE3800

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For proper scale operation, the SCLK frequency must be programmed so that:

SCL_PTR_POST_L

SCL_PTR_POST_U

0A26

0A27

[7:0]

[3:0]

The minimum difference of the write pointer and the last

of three read pointers; updated every frame

LSB = 4 pixels

SCL_CONTROL

0A28

R/W

[4]

allow trigger delay count to be retriggered by SMUX vtrig

(normal = 0)

R/W

[3]

use two tap vertical filter

0*: in hpixel <= 1024

1: in_hpixel > 1024

ptr_pre is invalid in this case

R/W

[2]

allow output sequencer to be retriggered before

vtotal_min (normal = 0)

R/W

[1]

completes the current frame then stops the sequencer.

Poll the vcount register to determine when frame has

stopped.

R/W

[0]

enable scaler timing engine (output sequencer)

SCL_VCOUNT

0A29

[7:0]

output sequencer vertical counter >> 4

SCL_HTOTAL_L

SCL_HTOTAL_U

0A2A

0A2B

R/W

[7:0]

[3:0]

desired output htotal - 1

out_htotal should be even

note: out_henab should be a multiple of 4 for RSDS dual

SCL_VTOTAL_MIN_L

SCL_VTOTAL_MIN_U

0A2C

0A2D

R/W

[7:0]

[3:0]

minimum vcount before a new frame can be started

SCL_VTOTAL_MAX_L

SCL_VTOTAL_MAX_U

0A2E

0A2F

R/W

[7:0]

[3:0]

vcount at which the output sequencer will self trigger to

maintain a minimum frame rate to the panel

SCL_TRIGGER_DLY_L

SCL_TRIGGER_DLY_M

SCL_TRIGGER_DLY_U

0A30

0A31

0A32

R/W

[7:0]

[3:0]

time in xclks from SMUX vtrig to when vcount/hcount of

the output sequencer are reset to 0,0.

SCL_LINE_START_L

SCL_LINE_START_U

0A33

0A34

R/W

[7:0]

[3:0]

pipe start value

= 4.5 -origin_hpos*4096/scale_factor_h -(21.5+5*4096/

pipe_rate)*sclk_period/dotclk_period

If pipe_rate = 0, use 4096.

SCL_CONTEXT_0

0A35

R/W

[6:1]

context sharp offset

R/W

[0]

enable context function (normal)

SCL_CONTEXT_1

0A36

R/W

[7:6]

context smooth slope (recommended = 1, 2, 3)

R/W

[5:4]

context sharp slope

R/W

[3:0]

context sharp clip

Table 23: Scale Registers (Sheet 3 of 3)

Addr

R/W

Bits

Rst

Description

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