công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

ADE3800XT bảng dữ liệu(PDF) 21 Page - STMicroelectronics

tên linh kiện ADE3800XT
Giải thích chi tiết về linh kiện  Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters
PDF  138 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ADE3800XT bảng dữ liệu(HTML) 21 Page - STMicroelectronics

Back Button ADE3800XT Datasheet HTML 17Page - STMicroelectronics ADE3800XT Datasheet HTML 18Page - STMicroelectronics ADE3800XT Datasheet HTML 19Page - STMicroelectronics ADE3800XT Datasheet HTML 20Page - STMicroelectronics ADE3800XT Datasheet HTML 21Page - STMicroelectronics ADE3800XT Datasheet HTML 22Page - STMicroelectronics ADE3800XT Datasheet HTML 23Page - STMicroelectronics ADE3800XT Datasheet HTML 24Page - STMicroelectronics ADE3800XT Datasheet HTML 25Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 138 page
background image
21/138
ADE3800
Register Description by Block
4.3
Analog-to-Digital Converter (ADC)
The Analog-to-Digital block has the following features:
● Supports input clocks up to 140MHz (SXGA 75Hz)
● Adjustable analog amplifier bandwidth
● Differential RGB input path for noise immunity
● Built-in Sync-on-Green support
● Individual RGB clock delay control
● Power down control
● Linear and independent Gain/Offset adjustment.
GAIN CONTROL
Red, Green, and Blue channels have independent control registers: ANA_ADC_RED_0,
ANA_ADC_GRN_0, and ANA_ADC_BLU_0, respectively.
FSYN_FM_AMPLITUDE
0855
R/W
[7:0]
00
frequency modulation amplitude
LSB = 4.5ps
FSYN_FM_PERIODX64
0856
R/W
[7:0]
80
frequency modulation period
LSB = 1.184us
FSYN_PULSE_HIGH_EXT
0857
R/W
[7]
00
enable pulse extend
0*: disabled
1: enabled
R/W
[2:0]
pulse extend value
LSB = 0.3ns (typ)
Table 11: FSYN_PR_SK Registers
Register Name
Addr
Mode
Bits
Rst
Description
FSYN_PR_SK_0
FSYN_PR_SK_1
0860
0861
R/W
R/W
[7:0]
[7:0]
00
00
sclk phase rate
= 2^15 * xclk_freq / sclk_freq
Set sclk = 140MHz
i.e. FSYN_PR_SK_1/0 = 18AFh @ xclk = 27MHz
Table 12: Clock Relationship
1 ppc
2 ppc
FSYN_OUTCLK_FREQ
2x DOTCLK_FREQ
DOTCLK_FREQ
DOTCLK SOURCE SEL
FSYN_OUTCLK_DIV2 (half speed)
FSYN_OUTCLK (full speed)
GLBL_CLK_SRC_SEL_0[6:4]
2
3
GLBL_CLK_SRC_SEL_1[6:4]
3
3
FSYN_PR_OTCLK
2^21 * XCLK_FREQ / 2x DOTCLK_FREQ
2^21 * XCLK_FREQ / DOTCLK_FREQ
Table 10: FSYN Frequency Synthesizer Registers (Sheet 2 of 2)
Register Name
Addr
Mode
Bits
Rst
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com