STA680 datasheet(30/43 Pages) STMICROELECTRONICS

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Digital I/O and memory interfaces

STA680

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5.3.4

Audio sample rate converter (ASRC)

The STA680 supports various external host audio interfaces. The audio sample rate

converter is designed to interface the audio output to systems with local master audio clock

sources.

Output sample rates of 44,100 (± 10 Hz), 45,600 (± 15 Hz) and 48,000 (± 15 Hz) are

acceptable. Total harmonic distortion plus noise (THD+N) at 1 kHz is greater than 85 dB

down (0.0056%).

One stereo channel (i.e. single ADAT line) either from the input SAI or from the output SAI

can be used with the audio sample rate converter.

In applications where the STA680 supplies the master clock to the audio D/A converter, the

ASRC will be bypassed.

5.4

Serial peripheral interfaces (SPI)

The STA680 provides three serial peripheral interfaces, each one intended for a different

and specific purpose:

●

SPI1 - The first SPI is intended for communicating with the Host Microcontroller.

Alternatively to this purpose can be also the Host Micro I2C Interface (see

Chapter 5.4.1)

●

SPI2 - The second SPI has been taught to interface the STA680 with the external an

external flash typically used to store the application code.

●

SPI3 - The third SPI allow the HD Radio decoder to control an external SD/MMC card.

For master mode the SPI clock frequency is a divide down by n of the internal peripheral

clock frequency, where n is an integer number comprised between 2 and 65536. The

maximum SPI clock frequency in master mode is 25 MHz.

For slave mode the maximum input frequency value accepted for the SPI clock from an

external device is a function of the internal peripheral clock.

In particular the maximum frequency is

Figure 11 shows timing diagrams and waveform for the three SPI.

SPI

perif

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