STA680 datasheet(22/43 Pages) STMICROELECTRONICS

22 / 43 page

Operation and general remarks

STA680

22/43

Figure 7 shows a simplified version of the internal clock generation unit.

Figure 7.

Clock generation unit

Some remarks on the choice of the clock input pin must be done:

●

OSC_IN is always a 1.8 V input pin.

●

CLK_IN, BB1_BCK and AUDIO_IN_ABCK are 3.3 V pins when the LQFP package is

selected while they can be configured as a 3.3 V or 1.8 V pins if the LFBGA is chosen

(see Chapter 3.4)

●

When the clock is fed through CLK_IN pin, the OSC_IN pin must be connected to

ground. Similarly if the clock is fed using CLK_IN pin then the OSC_IN pin must be

connected to ground.

●

The BB1_BCK pin is the bit clock of the digital interface to the base-band Tuner, so to

fed the reference clock through this pin the selected clock frequency must be chosen

accordingly to the Primary base-band Interface settings (see Chapter 5.2):

–

10.4 MHz = 16 * 2 * 650 kHz

→ BBI set to 650 Ksample/s

–

10.8 MHz = 16 * 2 * 675 kHz

→ BBI set to 675 Ksample/s

–

14.112 MHz = 16 * 2 * 882 kHz

→ BBI set to 882 Ksample/s

●

The AUDIO_IN_ABCK is the bit clock of the digital audio input interface to the Tuner.

When this pin is selected as clock source the STA680 Input Serial Audio Interface (see

Chapter 5.3.2) must be set according to following specification:

–Slave mode

–

Input sample rate = 45.6 kHz

–

Word length = 32 bit

With this settings the reference clock frequency is 2.9184 MHz = 32 * 2 * 45.6 kHz.

Internal

Oscillator

OSCI_OUT

OSCI_IN

BB1_BCK

AUDIO_IN_ABCK

CLK_IN

Encoder

OSC_EN

CLK_SEL

Core Clock

PLL

Peripheral

Clock PLL

PLL Settings

Clock to Cores

Clock to Peripherals

AC00712

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