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STA335BWS bảng dữ liệu(PDF) 62 Page - STMicroelectronics

tên linh kiện STA335BWS
Giải thích chi tiết về linh kiện  2.1-channel high-efficiency digital audio system
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STA335BWS bảng dữ liệu(HTML) 62 Page - STMicroelectronics

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Application
STA335BWS
62/68
7
Application
7.1
Application schematic and power supplies
Figure 17 shows a circuit diagram of a typical application for STA335BWS. Particular care
has to be given to the layout of the PCB, especially the power supplies. The 3.3
Ω resistors
on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This
helps to prevent unwanted oscillation on the digital portion of the device due to inductive
tracks of the PCB. This same rule is also be applied to all the decoupling capacitors in order
to limit any kind of spikes on all the supplies.
Figure 17.
Application schematic
7.2
PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the
best performances from the device in general application. Please be noted that the ground
of this filter scheme has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, please take into account that the greater is the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
100nF
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
TW
EAPD
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
DDX3B
DDX3A
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
8
OUT2A
9
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
DDX3B
17
DDX3A
18
EAPD/4B
19
TWARN/4A
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
100nF
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
8
OUT2A
9
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
DDX3B
17
DDX3A
18
EAPD/4B
19
TWARN/4A
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
BEAD
BEAD
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG
100nF
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
TW
EAPD
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
DDX3B
DDX3A
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
8
OUT2A
9
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
DDX3B
17
DDX3A
18
EAPD/4B
19
TWARN/4A
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
100nF
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
8
OUT2A
9
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
DDX3B
17
DDX3A
18
EAPD/4B
19
TWARN/4A
20
VDD_DIG
21
GND_DIG
22
PWRDN
23
VDD_PLL
24
FILTER_PLL
25
PLL_GND
26
XTI
27
BICKI
28
LRCKI
29
SDI
30
RESET
31
INT_LINE
32
SDA
33
SCL
34
GND_DIG
35
VDD_DIG
36
OUT1B
DATA
PLL_FILT
OUT1A
10K
BEAD
BEAD
BEAD
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG



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