STA323W datasheet(38/77 Pages) STMICROELECTRONICS

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STA323W

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The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs). The correlation between the input clock and the input sample rate is

determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx

bits determine the PLL factor generating the internal clock and the IR bit determines the

oversampling ratio used internally.

7.1.2

Interpolation ratio select

The STA323W has variable interpolation (re-sampling) settings such that internal

processing and DDX output rates remain consistent. The first processing block interpolates

by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2.

The IR bits determine the re-sampling ratio of this interpolation.

Table 15.

IR and MCS settings for input sample rate and clock rate

Input sample rate

fs (kHz)

MCS[2:0]

000

001

010

011

100

101

32, 44.1, 48

768 * fs

512 * fs

384 * fs

256 * fs

128 * fs

576 * fs

88.2, 96

384 * fs

256 * fs

192 * fs

128 * fs

64 * fs

176.4, 192

384 * fs

256 * fs

192 * fs

128 * fs

64 * fs

Table 16.

Interpolation ratio select

Bit

R/W

RST

Name

Description

4:3

IR[1:0]

Selects internal interpolation ratio based on input I2S sample

frequency

Table 17.

IR bit settings as a function of input sample rate

Input sample rate fs (kHz)

IR[1, 0]

1st stage interpolation ratio

2 times over-sampling

44.1

2 times over-sampling

88.2

Pass-Through

176.4

Down-sampling by 2

192

Down-sampling by 2

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