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STA323W bảng dữ liệu(PDF) 72 Page - STMicroelectronics

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STA323W bảng dữ liệu(HTML) 72 Page - STMicroelectronics

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8.10.3
PLL unlock indicator
Under normal conditions (with the correct clock) the PLL is locked into an internal clocking
frequency. However, if the clock is insufficient or if it is abruptly lost, the PLL lock state is lost
and this information is relayed to the user via setting the PLLUL bit of the Status register
to 1. As soon as the PLL reverts back to a locked state, this bit is set to 0.
Table 73.
PLL unlock indicator
Bit
R/W
RST
Name
Description
7RO
0
PLLUL
0: normal operation (PLL is in a locked state)
1: PLL unlock is detected (due to probable clock loss)



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