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STA323W bảng dữ liệu(PDF) 11 Page - STMicroelectronics |
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STA323W bảng dữ liệu(HTML) 11 Page - STMicroelectronics |
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11 / 77 page ![]() STA323W Description 11/77 1.1 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In these blocks, up to four user-defined Biquads can be applied to each of the two channels. Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be implemented by means of configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow diagram through the EQ block 1.2 Output options Figure 4. Output power stage configurations pre-scale High pass BQ#1 Re-sampled input Treble Bass filter To mix filter BQ#2 BQ#3 BQ#4 De- emphasis filter If CxTCB = 0 BTC: bass boost/cut TTC: treble boost/cut If DEMP = 1 4 biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto loudness if AMEQ = 10 If HPB= 0 If DSPB = 0 and CxEQB = 0 Half bridge Half bridge Half bridge Half bridge Channel 1 Channel 2 OUT2A OUT2B OUT1A OUT1B Half bridge Half bridge Half bridge Half bridge Channel 2 Channel 3 OUT2A OUT2B OUT1A OUT1B Channel 1 Half bridge Half bridge Half bridge Half bridge Channel 3 OUT2A OUT2B OUT1A OUT1B 2-channel (full bridge) configuration, register bits OCFG[1:0] = 00 2.1-channel configuration, register bits OCFG[1:0] = 01 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 The setup register is Configuration register F (address 0x05) on page 48 |
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