STA308A datasheet(21/63 Pages) STMICROELECTRONICS

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STA308A

Registers

21/63

7.2

7.2.1

Configuration register A (0x00)

The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4

kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:

65.536 MHz for 32 kHz

90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD

98.304 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs). The relationship between the input clock and the input sample rate is

determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits

determine the PLL factor generating the internal clock and the IRn bits determine the

oversampling ratio used internally.

Interpolation ratio select

The STA308A has variable interpolation (oversampling) settings such that internal

processing and DDX output rates remain consistent. The first processing block interpolates

by either 4 times, 2 times, or 1 time (pass-through).

The oversampling ratio of this interpolation is determined by the IR bits.

COS1

COS0

DSPB

IR1

IR0

MCS2

MCS1

MCS0

Bit

RST

Name

Description

0RW

MCS0

Master clock select: selects the ratio between the

input I2S sample frequency and the input clock.

1RW

MCS1

2RW

MCS2

Input sample rate

fs (kHz)

MCS[2:0]

1XX

011

010

001

000

32, 44.1, 48

128 * fs

256 * fs

384 * fs

512 * fs

768 * fs

88.2, 96

64 * fs

128 * fs

192 * fs

256 * fs

384 * fs

176.4, 192

64 * fs

128 * fs

192 * fs

256 * fs

384 * fs

DSD

2 * fs

4 * fs

6 * fs

8 * fs

10 * fs

Bit

RST

Name

Description

IR0

Interpolation ratio select: selects internal

interpolation ratio based on input I2S sample

frequency

4RW

IR1

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