ORLI10G datasheet(3/80 Pages) LATTICE

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Lattice Semiconductor

ORCA ORLI10G Data Sheet

– New LUT structure allows ﬂexible combinations of LUT4, LUT5, new LUT6, 4 : 1 MUX, new 8 : 1 MUX, and

ripple mode arithmetic functions in the same PFU.

– 32 x 4 RAM per PFU, conﬁgurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in

only eight PFUs) using the SLIC decoders as bank drivers.

– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast

internal routing, which reduces routing congestion and improves speed.

– Flexible fast access to PFU inputs from routing.

– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-

tions, with the option to register the PFU carry-out.

• Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over

previous architectures.

• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in

faster routing times with predictable and efﬁcient performance.

• SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PAL™-like AND-OR-INVERT (AOI) in each pro-

grammable logic cell.

• New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane

enables. Each embedded RAM block can be conﬁgured as:

– 1—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.

– 1—256 x 36 (dual-port, one read/one write).

– 1—1k x 9 (dual-port, one read/one write).

– 2—512 x 9 (dual-port, one read/one write for each).

– 2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).

– Supports joining of RAM blocks.

– Two 16 x 8-bit Content Addressable Memory (CAM) support.

– FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9.

– Constant multiply (8 x 16 or 16 x 8).

– Dual variable multiply (8 x 8).

• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),

embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-

in system registers that act as the control and status center for the device.

• Built-in testability:

– Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only.

– Programming and readback through boundary-scan port compliant to IEEE Draft 1532:D1.7.

– TS_ALL testability function to 3-state all I/O pins.

– New temperature-sensing diode.

• Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provides optimum clock

modiﬁcation and conditioning for phase, frequency, and duty cycle from 20 MHz up to

420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x is possible.

• New cycle stealing capability allows a typical 15% to 40% internal speed improvement after ﬁnal place and route.

This feature also supports compliance with many setup/hold and clock-to-out I/O speciﬁcations, and may provide

reduced ground bounce for output buses by allowing ﬂexible delays of switching output buffers.

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