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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ORLI10G bảng dữ liệu(PDF) 39 Page - Lattice Semiconductor |
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ORLI10G bảng dữ liệu(HTML) 39 Page - Lattice Semiconductor |
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39 / 80 page  Lattice Semiconductor ORCA ORLI10G Data Sheet 39 Recommended Board Level Routing For ORLI10G XSBI 10G Interface The Transmit XSBI port sends clock and data simultaneously as shown in Figure 21. Figure 21. Clock and Data signals from the TX The correct clock and data relation required for the XSBI receiver is to have the clock centered in the data eye (as shown in Figure 22). Figure 22. Clock and Data Signals at the Receiver In order to achieve the needed clock and data relationship at the receiver as shown in Figure 21, it is necessary to swap the P and N clock terminals on the board. This is illustrated in Figure 23. The board level signal swap on the receiver clock pins effectively inverts the clock phase at the receiving chip creating the correct clock data relation- ship shown in Figure 22. N P CLOCK N P DATA t period 1500pS = N P CLOCK N DATA P |
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