STTS424E02BDA3F datasheet(30/51 Pages) STMICROELECTRONICS

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SPD EEPROM operation

STTS424E02

30/51

Figure 10.

Result of setting the write protection

5.4

Setting the write protection

The Write Control (WC) is tied Low, hence the write protection of the memory array is

dependent on whether software write-protection has been set.

Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh)

to be write protected irrespective of subsequent states of the Write Control (WC) signal.

Software write-protection is handled by three instructions:

●

SWP: Set write protection

●

CWP: Clear write protection

●

PSWP: Permanently set write protection

The level of write-protection (set or cleared) that has been defined using these instructions,

remains defined even after a power cycle.

Table 21.

Operating modes

Mode

RW bit

WC(1)

X = VIH or VIL.

Bytes

Initial sequence

Current address read

START, device select, RW = 1

Random address read

START, device select, RW = 0, address

reSTART, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

Byte write

START, device select, RW = 0

Page write

≤ 16

START, device select, RW = 0

Default EEPROM memory area

state before write access

to the Protect Register

AI01936C

Standard

Array

FFh

Standard

Array

80h

7Fh

00h

Standard

Array

FFh

Write

Protected

Array

80h

7Fh

00h

State of the EEPROM memory

area after write access

to the Protect Register

Memory

Area

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