STTS424E02BDA3F datasheet(28/51 Pages) STMICROELECTRONICS

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SPD EEPROM operation

STTS424E02

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SPD EEPROM operation

5.1

2 Kb SPD EEPROM operation

The 2 Kbit serial EEPROM is able to lock permanently the data in its first half (from location

00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (Dual in

line Memory Modules) with Serial Presence Detect. All the information concerning the

DRAM module configuration (such as its access speed, its size, its organization) can be

kept write protected in the first half of the memory.

The first half of the memory area can be write-protected using two different software write

protection mechanisms. By sending the device a specific sequence, the first 128 bytes of

the memory become write protected: permanently or resetable.

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are

organized as 256x8 bits.

I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line.

The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the

I2C bus definition to access the memory area and a second Device Type Identifier Code

(0110) to define the protection. These codes are used together with the voltage level applied

on the three chip enable inputs (A2, A1, A0). These input signals are used to set the value

that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device

Select Code. In the end application, A0, A1 and A2 must be directly (not through a pull-up or

pull-down resistor) connected to VDD or VSS to establish the Device Select Code. When

these inputs are not connected, an internal pull-down circuitry makes (A0,A1,A2) = (0,0,0).

The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction

(refer to Table 20: Device select code).

The device behaves as a slave device in the I2C protocol, with all memory operations

synchronized by the serial clock. Read and Write operations are initiated by a START

condition, generated by the bus master. The START condition is followed by a Device Select

Code and RW bit (as described in Table 20: Device select code), terminated by an

acknowledge bit.

When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.

5.2

Internal device reset - SPD EEPROM

In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)

circuit is included.

At Power-up (phase during which VDD is lower than VDDmin but increases continuously), the

device will not respond to any instruction until VDD has reached the Power On Reset

threshold voltage (this threshold is lower than the minimum VDD operating voltage defined in

Table 2: AC SMBus and I2C compatibility timings). Once VDD has passed the POR

threshold, the device is reset.

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