STLC1502 datasheet(2/81 Pages) STMICROELECTRONICS

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STLC1502

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Data Modem: V.34 datapump

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Rate selection

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High performance voice activity detector (VAD)

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Comfort noise generator (CNG)

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G.165 32 ms Line & acoustic echo canceller

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Low latency system implementation

Figure 1: Block diagram

3.0 SYSTEM OVERVIEW

Three main blocks can be identified in the device architecture: ARM domain, the D950 domain and the

Clocks tree domain.

3.1 ARM7 domain

The ARM domain is a multibus microprocessor system based on the ARM7TDMI processor.

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The system bus is based on the Advanced Microcontroller Bus Architecture (AMBA) that includes

two distinct buses:

• The Advanced High performance Bus (AHB) for high performances system modules

• The Advanced Peripheral Bus (APB) for low power peripherals.

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A high speed 32 bit data bus is provided to connect external memories.

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A controller for external static memory (ESM) and a controller for external dynamic memory (EDM)

are provided.

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Static memories, like FLASH EPROM, SRAM and dynamic memories like EDO, SDRAM, can be

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