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C167CS-L bảng dữ liệu(PDF) 21 Page - Infineon Technologies AG |
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C167CS-L bảng dữ liệu(HTML) 21 Page - Infineon Technologies AG |
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21 / 81 page ![]() C167CS-4R C167CS-L Data Sheet 17 V2.2, 2001-08 Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167CS’s instructions can be executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. Figure 4 CPU Block Diagram MCB02147 CPU SP STKOV STKUN Instr. Reg. Instr. Ptr. Exec. Unit 4-Stage Pipeline MDH MDL PSW SYSCON Context Ptr. Mul/Div-HW R15 R0 General Purpose Registers Bit-Mask Gen Barrel - Shifter ALU (16-bit) Data Page Ptr. Code Seg. Ptr. Internal RAM R15 R0 ROM 16 16 32 BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4 ADDRSEL 3 ADDRSEL 2 ADDRSEL 1 |
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