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C167CS-L bảng dữ liệu(PDF) 63 Page - Infineon Technologies AG |
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C167CS-L bảng dữ liệu(HTML) 63 Page - Infineon Technologies AG |
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63 / 81 page ![]() C167CS-4R C167CS-L Data Sheet 59 V2.2, 2001-08 AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Figure 13 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 40 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). Table 12 External Clock Drive Characteristics Parameter Symbol Direct Drive 1:1 Prescaler 2:1 PLL 1:N Unit min. max. min. max. min. max. Oscillator period tOSC SR 25 – 20 – 371) 1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 5001) ns High time2) 2) The clock input signal must reach the defined levels V IL2 and VIH2. t1 SR 123) 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f CPU) in direct drive mode depends on the duty cycle of the clock input signal. – 5 – 10 – ns Low time2) t2 SR 123) – 5 – 10 – ns Rise time2) t3 SR – 8 – 5 – 10 ns Fall time2) t4 SR – 8 – 5 – 10 ns MCT02534 3 t 4 t VIH2 VIL V DD 0.5 1 t 2 t OSC t |
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