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V54C365804VC bảng dữ liệu(PDF) 1 Page - Mosel Vitelic, Corp |
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V54C365804VC bảng dữ liệu(HTML) 1 Page - Mosel Vitelic, Corp |
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1 / 54 page ![]() MOSEL VITELIC 1 V54C365804VC HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 V54C365804VC Rev. 0.6 September 1999 PRELIMINARY 7 75 8PC 8 System Frequency (fCK) 143MHz 133MHz 125 MHz 125 MHz Clock Cycle Time (tCK3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 6 ns 7 ns Clock Access Time (tAC2) CAS Latency = 2 5.5 ns 6 ns 6 ns 7 ns Features s 4 banks x 2Mbit x 8 organization s High speed data transfer rates up to 143 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Data Mask for Read/Write Control s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 2, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge Command s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 54 Pin 400 mil TSOP-II s LVTTL Interface s Single +3.3 V ±0.3 V Power Supply Description The V54C365804VC is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 8. The V54C365804VC achieves high speed data transfer rates up to 143 MHz by employing a chip architec- ture that prefetches multiple bits and then synchro- nizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an inter- leaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power Temperature Mark T 7 75 8PC 8 Std. L 0 °C to 70°C • • • • • • • Blank |
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Mô tả tương tự - V54C365804VC |
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