TAS5705PAPRG4 datasheet(28/71 Pages) TI

tên linh kiện	TAS5705PAPRG4

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Left-Justified

SCLK

32Clks

LRCLK

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelLeft-JustifiedStereoInput

T0034-02

MSB

LSB

SCLK

TAS5705

SLOS549 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it

is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,

48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK

toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused

trailing data-bit positions.

NOTE: All data presented in 2s-complement form with MSB first.

Figure 31. Left-Justified 64-fS Format

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