DSP56F826 datasheet(18/60 Pages) FREESCALE

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56F827 Technical Data, Rev. 12

Freescale Semiconductor

PCS2

Input/Output

Programmable Chip Select - PCS 2-7 is asserted low for external peripheral

chip select.

PCS3

Input/Output

PCS4

Input/Output

PCS5

Input/Output

PCS6

Input/Output

PCS7

Input/Output

ANA0

Input

ANA0

–9—Analog inputs to ADC

ANA1

Input

ANA2

Input

ANA3

Input

ANA4

Input

ANA5

Input

ANA6

Input

ANA7

Input

ANA8

Input

ANA9

Input

VREFN

Input

ADC Reference—This pin is connected to the negative side of the ADC input

range. This pin requires a 0.1

μF ceramic capacitor to VSSA and a start-up time

of 25ms, prior to beginning conversions.

VREFP

Input

ADC Reference—This pin is connected to the positive side of the ADC input

range. This pin requires a 0.1

μF ceramic capacitor to VSSA and a start-up time

of 25ms, prior to beginning conversions.

VREFMID

Input

ADC Reference—This pin isconnected to the center of the ADC input range.

This pin requires a 0.1

μF ceramic capacitor to VSSA and a start-up time of

25ms, prior to beginning conversions.

VREFLO

Input

ADC Reference—These pins are Negative Reference for ADC and are

generally connected to a VSSA.

VREFHI

Input

ADC Reference—These pins are Positive Reference for ADC and are

generally connected to a 3.3V Analog (VDDA_ADC) supply.

IRQA

Input

(Schmitt)

External Interrupt Request A—The IRQA input is a synchronized external

interrupt request that indicates that an external device is requesting service. It

can be programmed to be level-sensitive or negative-edge-triggered. If

level-sensitive triggering is selected, an external pull-up resistor is required for

wired-OR operation.

If the processor is in the Stop state and IRQA is asserted, the processor will

exit the Stop state.

Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

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