DSP56F826 datasheet(33/60 Pages) FREESCALE

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External Bus Asynchronous Timing

56F827 Technical Data, Rev. 12

Freescale Semiconductor

3.6.4

Phase Locked Loop Timing

3.7 External Bus Asynchronous Timing

Table 3-9 PLL Timing

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 4MHz input crystal.

fosc

MHz

PLL output frequency2

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the

User Manual. ZCLK = fop

fout/2

—

110

MHz

PLL stabilization time 3-40o to +85oC

3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

tplls

—1

Table 3-10 External Bus Asynchronous Timing1, 2

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Max

Unit

Address Valid to WR Asserted

tAWR

6.5

—

WR Width Asserted

Wait states = 0

Wait states > 0

tWR

7.5

(T*WS) + 7.5

—

WR Asserted to D0–D15 Out Valid

tWRD

—T + 4.2

Data Out Hold Time from WR Deasserted

tDOH

4.8

—

Data Out Set Up Time to WR Deasserted

Wait states = 0

Wait states > 0

tDOS

2.2

(T*WS) + 6.4

—

RD Deasserted to Address Not Valid

tRDA

0—

Address Valid to RD Deasserted

Wait states = 0

Wait states > 0

tARDD

18.7

(T*WS) + 18.7

—

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