16

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Write Interrupted by a Write

A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that

separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are over-

ridden by the new address and data will be written into the device until the programmed burst length is satisfied.

0

1

2

3

4

5

6

7

8

CK

CK

Command

NOP

NOP

NOP

NOP

NOP

DQS

DQs

Figure.10 Write interrupted by a write timing

< Burst Length=4 >

WRITE A

NOP

WRITE B

NOP