RMLD232UAW datasheet(15/50 Pages) EMLSI

15 / 50 page

Rev 0.7

64Mb Low Power DDR SDRAM

Advanced

Read Interrupted by a Precharge

A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge

intervals. A precharge command to output disable latency is equivalent to the CAS latency.

when a burst Read command is issued to a DDR SDRAM, a precharge command may be issued to the same bank before the Read

burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a

new Bank Activate command may be issued to the same bank.

1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the

rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate

command may be issued to the same bank after tRP (RAS Precharge time).

2. when a Precharge command interrupts a Read burst operation, the precharge command may be given on the rising clock edge

which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data

word has been output, the output buffers are tristated, A new Bank Activate command may be issued to the same bank after tRP.

3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP

begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During

Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external

Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.

4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a

Precharge command and a new Bank Activate command to the same bank equals tRP/tCK(where tCK is the clock cycle time)

with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to x .5 is not possible since the

Precharge and Bank Activate commands can only be given on a rising clock edge). In all cases, a Precharge operation cannot

be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with

autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same

timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.

Command

NOP

Precharge

NOP

DQS

DQs

Figure.9 Read interrupted by a precharge timing

< Burst Length=8, CAS Latency=3 >

READ

tAC

Dout 0 Dout 1

tRPRE

CAS Latency=3

NOP

Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7

Interrupted by precharge

1tCK

NOP

RMLD232UAW bảng dữ liệu(PDF) 15 Page - Emerging Memory & Logic Solutions Inc

RMLD232UAW bảng dữ liệu(HTML) 15 Page - Emerging Memory & Logic Solutions Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bảng dữ liệu tải về

Link URL