ST92141 datasheet(154/179 Pages) STMICROELECTRONICS

154 / 179 page

154/179

ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)

CONTROL LOGIC REGISTER (CLR)

The Control Logic Register (CLR) manages the

ADC’s logic. Writing to this register will cause the

current conversion to be aborted and the autoscan

logic to be re-initialized. CLR is programmable as

follows:

CONTROL LOGIC REGISTER (CLR)

R253 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:5 = SC[2:0]:

Start Conversion Address.

These 3 bits define the starting analog input chan-

nel (Autoscan mode). The first channel addressed

by SC[2:0] is converted, then the channel number

is incremented for the successive conversion, until

channel 7 (111) is converted. When SC2, SC1 and

SC0 are all set, only channel 7 will be converted.

Bit 4 = EXTG:

External Trigger Enable.

This bit is set and cleared by software.

0: External trigger disabled.

1: External trigger enabled. Allows a conversion

sequence to be started on the subsequent edge

of the external signal applied to the EXTRG pin

(when enabled as an Alternate Function).

Bit 3 = INTG:

Internal Trigger Enable.

This bit is set and cleared by software.

0: Internal trigger disabled.

1: Internal trigger enabled. Allows a conversion se-

quence to be started, synchronized by an inter-

nal signal (On-chip Event signal) from a Multi-

function Timer peripheral.

Both External and Internal Trigger inputs are inter-

nally ORed, thus avoiding Hardware conflicts;

however, the correct procedure is to enable only

one alternate synchronization input at a time.

Note: The effect of either synchronization mode is

to set the START/STOP bit, which is reset by hard-

ware when in SINGLE mode, at the end of each

sequence of conversions.

Requirements: The External Synchronisation In-

put must receive a low level pulse wider than an

INTCLK period and, for both External and On-Chip

Event synchronisation, the repetition period must

be greater than the time required for the selected

sequence of conversions.

Bit 2 = POW:

Power Up/Power Down.

This bit is set and cleared by software.

0: Power down mode: all power-consuming logic is

disabled, thus selecting a low power idle mode.

1: Power up mode: the A/D converter logic and an-

alog circuitry is enabled.

Bit 1 = CONT:

Continuous/Single.

0: Single Mode: a single sequence of conversions

is initiated whenever an external (or internal)

trigger occurs, or when the ST bit is set by soft-

ware.

1: Continuous Mode: the first sequence of conver-

sions is started, either by software (by setting

the ST bit), or by hardware (on an internal or ex-

ternal trigger, depending on the setting of the

INTG and EXTG bits); a continuous conversion

sequence is then initiated.

Bit 0 = ST:

Start/Stop.

0: Stop conversion. When the A/D converter is

running in Single Mode, this bit is hardware re-

set at the end of a sequence of conversions.

1: Start a sequence of conversions.

SC2

SC1

SC0

EXTG

INTG

POW

CONT

ST92141 bảng dữ liệu(PDF) 154 Page - STMicroelectronics

ST92141 bảng dữ liệu(HTML) 154 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL