ST72511R datasheet(32/164 Pages) STMICROELECTRONICS

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ST72311R, ST72511R, ST72512R, ST72532R

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INTERRUPTS (Cont’d)

Table 6. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never

be used in an interrupt routine.

Table 7. Interrupt Mapping

Instruction

New Description

Function/Example

HALT

Entering Halt mode

IRET

Interrupt routine return

Pop CC, A, X, PC

JRM

Jump if I1:0=11

I1:0=11 ?

JRNM

Jump if I1:0<>11

I1:0<>11 ?

POP CC

Pop CC from the Stack

Mem => CC

RIM

Enable interrupt (level 0 set)

Load 10 in I1:0 of CC

SIM

Disable interrupt (level 3 set)

Load 11 in I1:0 of CC

TRAP

Software trap

Software NMI

WFI

Wait for interrupt

Source

Block

Description

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET

Reset

N/A

Highest

Priority

Lowest

Priority

yes

FFFE h-FFFFh

TRAP

Software Interrupt

FFFCh-FFFDh

TLI

External Top Level Interrupt

MISCR2

yes

FFFA h-FFFBh

MCC/RTC

Main Clock Controller Time Base Interrupt

MCCSR

FFF8h-FFF9h

ei0

External Interrupt Port A3..0

N/A

FFF6h-FFF7h

ei1

External Interrupt Port F2..0

FFF4h-FFF5h

ei2

External Interrupt Port B3..0

FFF2h-FFF3h

ei3

External Interrupt Port B7..4

FFF0h-FFF1h

CAN

CAN Peripheral Interrupts

CANISR

FFEEh-FFE Fh

SPI

SPI Peripheral Interrupts

SPISR

FFECh-FFE Dh

TIMER A

TIMER A Peripheral Interrupts

TASR

FFEAh-FFEBh

TIMER B

TIMER B Peripheral Interrupts

TBSR

FFE8h-FFE 9h

SCI

SCI Peripheral Interrupts

SCISR

FFE6h-FFE 7h

EEPROM

EEPROM Interrupt

EECSR

FFE4h-FFE 5h

Not Used

FFE2h-FFE 3h

PWM ART

PWM ART Overflow Interrupt

ARTCSR

Yes

FFE0h-FFE 1h

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