ST72141K2 datasheet(70/132 Pages) STMICROELECTRONICS

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ST72141K

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MOTOR CONTROLLER (Cont’d)

Table 31. Multiplier Result

CONTROL REGISTER B (MCRB)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:6 = VR[1:0]:

BEMF/demagnetization Refer-

ence threshold

These bits select the VREF value as shown in the

following table.

Bit 5 = CPB*:

Compare Bit for Zero-crossing de-

tection.

0: Zero crossing detection on falling edge

1: Zero crossing detection on rising edge

Bit 4 = HDM*:

Hardware Demagnetization event

Mask bit

0: Hardware Demagnetization disabled

1: Hardware Demagnetization enabled

Bit 3 = SDM*:

Software Demagnetization event

Mask bit

0: Software Demagnetization disabled

1: Software Demagnetization enabled

Bits 2:0 = OS2*,OS[1:0]:

Operating output mode

Selection bits

Refer to the Step behaviour diagrams (Figure 40,

Figure 41, Figure 42) and Table 32.

These bits are used to configure the various PWM

output configurations.

Note: The OS2 bit is the only one with a preload

Table 32. Step Behaviour Summary

Note: For more details, see Step behaviour dia-

grams (Figure 40, Figure 41, and Figure 42).

* Preload bits, new value taken into account at

next C event.

DCB bit

Commutation Delay

MCOMP = MWGHT x MZPRV / 32

MCOMP = MWGHT x MZREG / 32

VR1

VR0

CPB*

HDM*

SDM*

OS2*

OS1

OS0

VR1

VR0

VREF Voltage threshold

0.2V

0.6V

1.2V

2.5V

Mode

OS2

bit

PWM after C

and before D

[1:0]

bits

PWM after D and

before C

Same as

after D and

before C

On even

channels

On odd

channels

Continuous

All active

channels

Alternate

On even

channels

On odd

channels

Alternate odd/even

All active

channels

Unused

On even

channels

On odd

channels

Alternate odd/even

All active

channels

On even

Channels

On even

channels

On odd

channels

Alternate odd/even

All active

channels

On odd

channels

On even

channels

On odd

channels

Alternate odd/even

All active

channels

Unused

On even

channels

On odd

channels

Alternate odd/even

All active

channels

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