ST70235A datasheet(21/28 Pages) STMICROELECTRONICS

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ST70235A

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Analog Front End Control Interface

The Analog Front End Interface is designed to be

connected to the ST70134 Analog Front End

component.

Transmit Interface

The 16 bit words are multiplexed on 4 AFTXD

output signals. As a result 4 cycles are needed to

transfer 1 word. Refer to table 1 for the bit/pin

allocation for the 4 cycles.

The first of 4 cycles is identified by the CLWD

signal. Refer to Figure 18.

The ST70235A fetches the 16 bit word to be

multiplexed on AFTXD from the Tx Digital

Front-End module.

Receive Interface

The 16 bit receive word is multiplexed on 4

AFRXD input signals. As a result 4 cycles are

needed to transfer 1 word.

Refer to Table 2 for the bit / pin allocation for the 4

cycles. The first of 4 cycles is identified by the

CLWD must repeat after 4 MCLK cycles.

Figure 18 : Transmit Word Timing Diagram

Figure 19 : Receive Word Timing Diagram

Cycle1

Cycle0

Cycle2

Cycle3

Test0

Test1

Test2

Test3

MCLK

CLWD

AFTXD

GP_OUT

Cycle1

Cycle0

Cycle2

Cycle3

Test0

Test1

Test2

Test3

MCLK

CLWD

AFRXD

GP_IN(0)

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