ST70235A

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Pin Description

Note

1. Active low signal

The ST70235A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted.

TxClk, RxClk, AC Electrical Characteristics

TxData, TxSOC, TxAddr, TxEnb, AC Electrical Characteristics

Note: Tx data hold time is 1.2ns. All the UTOPIA hold time are guarantee by design.

RxData, RxSOC, RxClav, TxClav, AC Electrical Characteristics

Name

Type

Meaning

Usage

Remark

TxClav

O

Transmit Cell

available

Signals to the ATM chip that the physical

layer chip is ready to accept a complete cell

Remains active for the entire

cell transfer

I

Transmit Enable

Signals to the ST70235A that TxData and

TxSOC are valid

TxClk

I

Transmit Byte Clock

Gives the timing signal for the transfer,

generated by ATM layer chip.

TxData

I

Transmit Data (8bits)

ATM cell data, from ATM layer chip to

ST70235A, byte wide. TxData [7] is the MSB.

TxSOC

I

Transmit Start of Cell

Identifies the cell boundary on TxData

TxData contains the first

valid byte of the cell.

I

Reference Clock

8kHz clock from the ATM layer chip

Symbol

Parameters

Minimum

Maximum

Unit

F

Clock frequency

1.5

25

MHz

Tc

Clock duty cycle

40

60

%

Tj

Clock peak to peak jitter

5

%

Trf

Clock rise fall time

4

ns

L

Load

100

pF

Symbol

Parameters

Minimum

Maximum

Unit

T5

Input set-up time to TxClk

10

ns

T6

Hold time to TxClk

1

ns

L

Load

100

pF

Symbol

Parameters

Minimum

Maximum

Unit

T7

Input set-up time to TxClk

10

ns

T8

Hold time to Tx Clk

1

ns

T9

Signal going low impedance to RxClk

10

ns

T10

Signal going High impedance to RxClk

0

ns

T11

Signal going low impedance to RxClk

1

ns

T12

Signal going High impedance to RxClk

1

ns

L

Load

100

pF