ST70235A

16/28

Figure 14 : Timing (Utopia 2 Receive Interface)

Pin Description

Note

1. Active low signal

When RxEnb is asserted, the ST70235A reads data from its internal fifo and presents it on RxData and

RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on

the rising edge of RxSOC on the rising edge of RxClk.

Name

Type

Meaning

Usage

Remark

RxClav

O

Receive Cell available

Signals to the ATM chip that the ST70235A

has a cell ready for transfer

Remains active for the entire

cell transfer

I

Receive Enable

Signals to the ST70235A that the ATM chip

will sample and accept data during next

clock cycle

RxData and RxSOC could be

tri-state when RxEnb* is

inactive (high). Active low

signal

RxClk

I

Receive Byte Clock

Gives the timing signal for the transfer,

generated by ATM layer chip.

RxData

O

Receive Data (8bits)

ATM cell data, from ST70235A chip to ATM

chip, byte wide. Rx Data [7] is the MSB.

RxSOC

O

Receive Start Cell

Identifies the cell boundary on RxData

Indicate to the ATM layer

chip that RxData contains

the first valid byte of a cell

O

Reference Clock

8 kHz clock transported over the network

Active low signal

1

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

N+3

1F

N-3

1F

N+1

1F

N-1

1F

N

1F

1F

N-1

1F

N-3

1F

N-3

1F

N+1

1F

N+2

N-3

N+1

N-1

N

N+3

N-1

N-3

N-3

N+1

RxClk

RxAddr

RxClav

RxEnb*

RxData

RxSOC

P41 P42

P43

P44

P45

P46

P47

P48

XX

H1

H2

H3

Cell transmission from:

PHY N

PHY N-3

Polling:

Polling

Detection

Selection

Polling