ST62T32B datasheet(47/86 Pages) STMICROELECTRONICS

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ST62T32B ST62E32B

4.3.1 CENTRAL COUNTER

The core of the 16 bit Auto-Reload Timer is a 16-

bit synchronous downcounter which accepts the

MCU internal clock through a prescaler with a pro-

grammable ratio (1/1, 1/4, 1/16).

The maximum time for downcounting is therefore

16 x Psc x Tclk where Psc is the prescaler ratio,

and Tclk the period of the main oscillator.

This down counter is stopped and its content kept

cleared as long as RUNRES bit is cleared.

4.3.1.1 Reload functions

The 16-bit down counter can be reloaded 3 differ-

ent ways:

At a zero overflow occurrence with the bit RELOAD

cleared: The counter is reloaded to FFFFh.

At a zero overflow occurrence with the bit

RELOAD set: The counter is reloaded with the val-

ue programmed in the RLCP register. For each

overflow, the transition between 0000h and the re-

load value (RLCP or FFFFh) is flagged through the

OVFFLG bit.

At an external event on pin CP1 or CP2 with the bit

RELOAD set: The counter is reloaded with the val-

ue programmed in the RLCP register.

As a consequence, the time between a timer re-

load and a zero overflow occurrence depends on

the value in RLCP when RELOAD bit is set. This

time is equal to (RLCP+1) x Psc x Tclk when

RELOAD bit is set, while it is 2

16 x Psc x Tclk when

RELOAD bit is cleared.

4.3.1.2 Compare functions

The value in the counter CT is continuously com-

pared to 0000h and to the value programmed into

the Compare Register CMP. The comparison

range to 0000h and CMP is defined by using the

MASK register to select which bits are used, there-

fore the comparisons performed are:

– MASK&CT =

? MASK&CMP.

– MASK&CT =

0000h.

When

a matched

comparison

to 0000h or

MASK&CMP occurs, the flags ZEROFLG and

COMPFLG are respectively set.

By using MASK values reported in Table 17, the

MASK register works as counter frequency multi-

plier for the compare functions. In that case posi-

tive masked comparison occur with a period of

(n+1) x Psc x Tclk where n is the position of the

most significant bit of MASK value.

Table 17. Recommended Mask Values

Note: Writing 0000h in MASK gives a period equal

to two times the prescaled period Psc x Tclk.

Figure 28. Flags Setting in Compare and Reload Functions

Hexadecimal

Binary

MSbit at 1

position,n

FFFFh

7FFFh

3FFFh

1FFFh

0FFFh

...

0007h

0003h

0001h

1111 1111 1111 1111

0111 1111 1111 1111

0011 1111 1111 1111

0001 1111 1111 1111

0000 1111 1111 1111

...

0000 0000 0000 0111

0000 0000 0000 0011

0000 0000 0000 0001

CMP

Counter

ZEROFLG

FFFFh

RLCP

Software Reset

OVFFLG

COMPFLG

Value CT

151

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