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ST62T32B bảng dữ liệu(PDF) 21 Page - STMicroelectronics |
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ST62T32B bảng dữ liệu(HTML) 21 Page - STMicroelectronics |
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21 / 86 page ![]() 21/86 ST62T32B ST62E32B CLOCK SYSTEM (Cont’d) Figure 12. Clock Circuit Block Diagram Figure 13. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD) Notes: 1. In this area, operation is guaranteed at the quartz crystal frequency. 2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least f OSG Min. 3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a f OSG. 4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f OSG. MAIN OSCILLATOR OSG LFAO M U X Core :13 :12 :1 TIMER 1 Watchdog POR fINT Main Oscillator off ADC ARTIMER 16 :6 M U X 1 2.5 3.5 4 4.5 5 5.5 6 8 7 6 5 4 3 2 Maximum FREQUENCY (MHz) SUPPLY VOLTAGE (VDD) 3 4 3 2 1 fOSG fOSG Min VR01807 125 |
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