PSD413A1 datasheet(91/123 Pages) STMICROELECTRONICS

91 / 123 page

PSD4XX Family

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCC

Supply Voltage

All Speeds

2.7

5.5

VIH

High Level Input Voltage

2.7 V < VCC < 5.5 V

.7 VCC

VCC +.5

VIL

Low Level Input Voltage

2.7 V < VCC < 5.5 V

–0.5

.3 VCC

VIH1

Reset High Level Input Voltage

(Note 1)

.8 VCC

VCC +.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–.5

.2 VCC –.1

VHYS

Reset Pin Hysteresis

0.3

VOL

Output Low Voltage

IOL = 20 µA, VCC = 2.7 V

0.01

0.1

IOL = 4 mA, VCC = 2.7 V

0.15

0.45

VOH

Output High Voltage

IOH = –20 µA, VCC = 2.7 V

2.9

2.99

IOH = –1 mA, VCC = 2.7 V

2.4

2.6

VSBY

SRAM Standby Voltage

2.7

VCC

ISBY

SRAM Standby Current

VCC = 0 V

0.5

µA

IIDLE

Idle Current (VSTBY Pin)

VCC > VSBY

–0.1

0.1

µA

VDF

SRAM Data Retention Voltage

Only on VSTBY

ISB

Standby Supply

Power Down Mode

CSI >VCC –.3 V (Note 2)

µA

Current

Sleep Mode

CSI >VCC –.3 V (Note 3)

µA

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

± 5

µA

ZPLD_TURBO = OFF,

See ISB

µA

ICC (DC)

Operating

f = 0 MHz (Note 4)

(Note 5)

Supply Current

ZPLD Only

ZPLD_TURBO = ON,

f = 0 MHz

200

400

µA/PT

ZPLD AC Base

(Note 4)

See

2.0

mA/MHz

Fig 38c

CMiser = ON

EPROM AC Adder

(8-Bit Bus Mode)

0.4

1.0

mA/MHz

ICC (AC)

All Other Cases

0.9

1.7

mA/MHz

(Note 5)

CMiser = ON and

0.7

1.3

mA/MHz

8-Bit Bus Mode

SRAM AC Adder

CMiser = ON and

mA/MHz

16-Bit Bus MoDe

CMiser = OFF

1.9

3.8

mA/MHz

13.9 DC Characteristics (ZPSD4XXV Versions)

(3.0 V ± 10% Versions)

NOTES: 1.

Reset input has hysteresis. VIL1 is valid at or below .2VCC –.1. VIH1 is valid at or above .8VCC.

CSI deselected or internal PD is active.

Sleep mode bit is set and internal PD is active.

See ZPLD ICC/Frequency Power Consumption graph for details.

IOUT = 0 mA.

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