PSD413A1 datasheet(78/123 Pages) STMICROELECTRONICS

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PSD4XX Family

System

Configuration

(cont.)

Data In

This Register is used to read the inputs on the port pins.

Control

“0” sets the corresponding port pin in Address Out Mode.

“1” sets the pin in MCU I/O Mode.

Data Out

Holds the output data in the MCU I/O Mode.

This register is used to control the data flow in the I/O ports.

Direction

“0” sets the corresponding pin as an input pin.

“1” sets the pin as an output pin.

Open Drain

“0” sets the corresponding pin driver as a CMOS driver.

“1” sets the pin driver as an Open Drain Driver.

PLD – I/O

A read only status register; a

“1” indicates the corresponding pin

is configured as a PLD pin.

Macrocell Out

This register holds the outputs of the GPLD macrocells.

Page Register

A 4-bit register that supports paging.

1. Configures the PSD4XX SRAM to be accessed by

“PSEN” as

program space (8031 design).

2. Enables the Peripheral I/O Mode of Port A.

PMMR0

Power management registers; enables the PSD4XX Power Down

PMMR1

Mode and other power saving configurations.

Table 23. Register Function

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