PSD413A2 datasheet(74/123 Pages) STMICROELECTRONICS

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PSD4XX Family

The PSD4XX

Architecture

(cont.)

Port Configuration

Pin Status

I/O Port

Unchanged

ZPLD Output

Depend on Inputs to the ZPLD

Address Out

Undefined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

Table 20. I/O Pin Status During Power Down And Sleep Mode

t Input Clock

The PSD4XX provides the option to turn off the clock inputs to save AC power

consumption. The clock input (CLKIN) is used as a source for driving the following

modules:

t ZPLD Array Clock Input

t ZPLD MacroCell Clock Flip Flop

t APD Counter Clock

During power down or if any of the modules are not being used the clock to these

modules should be disabled. To reduce AC power consumption, it is especially

important to disable the clock input to the ZPLD array if it is not used as part of a logic

equation.

The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK).

The ZPLD MacroCell Clock Input can be disabled by setting PMMR0 bit 6

(ZPLD RCLK). The Timer Clock can be disabled by setting PMMR0 bit 7

(TMR CLK). The APD Counter Clock will be disabled automatically if Power Down or

Sleep Mode is entered through the APD unit. The input buffer of the CLKIN input will be

disabled if bits 5 – 7 PMMR0 are set and the APD has overflowed.

PLD

Access

Propagation

Recovery

Time

Recovery

Delay

Time To

Normal

Operation

Access

Power Down

Normal t PD

No Access

t LVDV

(Note 1)

Sleep

t LVDV2

t LVDV3

No Access

t LVDV1

(Note 2)

(Note 3)

Summary of PSD4XX Timing and Standby Current During Power Down

and Sleep Modes

NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based

only on the ZPLD_Turbo Bit.

2. In Sleep Mode any input to the ZPLD will have a propagation delay of tLVDV2.

3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the

transition will have a propagation delay time of tLVDV3.

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