ST10F269Z2QX datasheet(36/161 Pages) STMICROELECTRONICS

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ST10F269Z2Qx

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6.1.1 - Features

6.1.1.1 - Enhanced Addressing Capabilities

– New addressing modes including a double indi-

rect addressing mode with pointer post-modifi-

cation.

– Parallel Data Move: this mechanism allows one

operand move during Multiply-Accumulate in-

structions without penalty.

– New transfer instructions CoSTORE (for fast ac-

cess to the MAC SFRs) and CoMOV (for fast

memory to memory table transfer).

6.1.1.2 - Multiply-Accumulate Unit

– One-cycle execution for all MAC operations.

– 16 x 16-bit signed/unsigned parallel multiplier.

– 40-bit signed arithmetic unit with automatic sat-

uration mode.

– 40-bit accumulator.

– 8-bit left/right shifter.

– Full instruction set with multiply and multiply-ac-

cumulate, 32-bit signed arithmetic and compare

instructions.

6.1.1.3 - Program Control

– Repeat Unit: allows some MAC co-processor in-

structions to be repeated up to 8192 times. Re-

peated instructions may be interrupted.

– MAC interrupt (Class B Trap) on MAC condition

flags.

Figure 10 : MAC Unit Architecture

Note: * Shared with standard ALU.

Operand 2

Operand 1

Control Unit

Repeat Unit

ST10 CPU

Interrupt

Controller

MSW

MRW

MAH

MAL

MCW

Flags MAE

Mux

8-bit Left/Right

Shifter

Mux

Sign Extend

16 x 16

Concatenation

signed/unsigned

Multiplier

40-bit Signed Arithmetic Unit

08000h

Scaler

GPR Pointers *

IDX0 Pointer

IDX1 Pointer

QR0 GPR Offset Register

QR1 GPR Offset Register

QX0 IDX Offset Register

QX1 IDX Offset Register

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