FXLS8961AF datasheet(58/101 Pages) NXP

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NXP Semiconductors

FXLS8961AF

3-Axis Low-g Accelerometer

• The INT2/BOOT_OUT pin only signals the boot process complete interrupt, signaled by a TPULSE-BOOT2

ms active low pulse (open-drain with external pull-up). Any other interrupt sources mapped to the INT2/

BOOT_OUT pin are ignored.

Bit

Name

DRDY_EN BUF_EN

SDCD_

OT_EN

SDCD_

WT_EN

ORIENT_

ASLP_EN BOOT_

DIS

WAKE_

OUT_EN

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 71. INT_EN register (address 20h) bit allocation

Field

Description

DRDY_EN

Data-ready interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as configured by the

setting made in INT_PIN_SEL.

Note: When BT_MODE = GND, SRC_DRDY bit and the signaled interrupt are cleared whenever one

or more of the VECM, and OUT_X/Y/Z registers are read. When BT_MODE = VDD, SRC_DRDY bit

is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read. However the data

ready interrupt is signaled for TPULSE-MOT s (5 ms typ) and it clears itself automatically. The current

data ready interrupt pulse is terminated when the device transitions into STANDBY mode before its

completion and therefore may not span for entire TPULSE-MOTs.

BUF_EN

Output data buffer interrupt output enable

0 Interrupt is not routed to the INTx output pins (default)

1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in

INT_

PIN_SEL.

SDCD_OT_EN

SDCD outside of thresholds interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is routed to either the INT1 or INT2 output pin as configured by the setting made in INT_

PIN_SEL.

SDCD_WT_EN

SDCD within thresholds interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in INT_

PIN_SEL.

ORIENT_EN

Orientation interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the

setting made in INT_PIN_SEL.

ASLP_EN

Auto-WAKE/SLEEP interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the

setting made in INT_PIN_SEL.

BOOT_DIS

Boot interrupt output disable

0 (default): Boot interrupt is enabled and routed to either the INT1 or INT2 output pin as determined

by the setting made in

INT_PIN_SEL. This interrupt is pulsed, with the polarity of the pulse

determined by the setting made in

SENS_CONFIG4[INT_POL].

Table 72. INT_EN register (address 20h) bit description

FXLS8961AF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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