NRF52811-QCAA-R datasheet(329/444 Pages) NORDIC

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Peripherals

ADDR

N-1

Figure 124: The TWI master writing data to a slave

The TWI master write sequence is stopped when the STOP task is triggered whereupon the TWI master

will generate a stop condition on the TWI bus.

6.23.5 Master read sequence

A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been

triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the

address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1).

The address must match the address of the slave device that the master wants to read from. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK = 1) generated by the slave.

After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the

master.

The TWI master will generate a RXDRDY event every time a new byte is received in the RXD register.

After receiving a byte, the TWI master will delay sending the ACK/NACK bit by stretching the clock until the

CPU has extracted the received byte, that is, by reading the RXD register.

The TWI master read sequence is stopped by triggering the STOP task. This task must be triggered before

the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before

generating the stop condition.

A typical TWI master read sequence is illustrated in The TWI master reading data from a slave on page

330. Occurrence 3 in this figure illustrates delayed processing of the RXDRDY event associated with RXD

byte B. In this scenario the TWI master will stretch the clock to prevent the slave from overwriting the

contents of the RXD register.

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