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RIVA128 bảng dữ liệu(PDF) 21 Page - STMicroelectronics

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RIVA128 bảng dữ liệu(HTML) 21 Page - STMicroelectronics

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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA 128
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5
PCI 2.1 LOCAL BUS INTERFACE
5.1
RIVA 128 PCI INTERFACE
The RIVA 128 supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host
interface is fully compliant with the 32-bit PCI 2.1 specification.
The Multimedia Accelerator supports PCI bus operation up to 33MHz with zero-wait state capability and
full bus mastering capability handling burst reads and burst writes.
Figure 10.
PCI interface pin connections
Table 3.
PCI bus commands supported by the RIVA 128
Bus master
Bus slave
Memory read and write
Memory read and write
Memory read line
I/O read and write
Memory read multiple
Configuration read and write
Memory read line
Memory read multiple
Memory write invalidate
PCICBE[3:0]#
PCIAD[31:0]
PCIFRAME#
32
4
PCIDEVSEL#
PCIIRDY#
PCITRDY#
PCISTOP#
PCIIDSEL
PCIREQ#
PCIGNT#
PCICLK
PCIRST#
PCIPAR
PCIINTA#
RIVA 128



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