MPC852T datasheet(34/80 Pages) FREESCALE

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MPC852T PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

Bus Signal Timing

Table 10 provides interrupt timing for the MPC852T.

Figure 24 provides the interrupt detection timing for the external level-sensitive lines.

Figure 24. Interrupt Detection Timing for External Level Sensitive Lines

Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.

Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines

Table 10. Interrupt Timing

Num

Characteristic1

1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as

level-sensitive. The IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT.

The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and have no direct

relation with the total system interrupt latency that the MPC852T is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (set up time)

6.00

I40

IRQx hold time after CLKOUT

2.00

I41

IRQx pulse width low

3.00

I42

IRQx pulse width high

3.00

I43

IRQx edge-to-edge time

× TCLOCKOUT

—

CLKOUT

IRQx

I39

I40

CLKOUT

IRQx

I41

I42

I43

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