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S5D3 bảng dữ liệu(PDF) 68 Page - Renesas Technology Corp

tên linh kiện S5D3
Giải thích chi tiết về linh kiện  S5D3 Microcontroller Group
PDF  89 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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S5D3 bảng dữ liệu(HTML) 68 Page - Renesas Technology Corp

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R01DS0328EU0120 Rev.1.20
Page 68 of 89
Dec 13, 2023
S5D3 Datasheet
2. Electrical Characteristics
Note:
These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during
A/D conversion, the values might not fall within the indicated ranges.
The use of ports 0 as digital outputs is not allowed when the 12-bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0, VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage
are stable.
Note 1.
The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2.
Values in parentheses indicate the sampling time.
Note 3.
When simultaneously using channel-dedicated sample-and-hold circuits in unit 0 and unit 1, see Table 2.35.
Channel-dedicated
sample-and-hold
circuits not in use
(AN100 to AN102)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.48
(0.267)*2
--
μs
Sampling in 16 states
Offset error
-
±1.0
±2.5
LSB
-
Full-scale error
-
±1.0
±2.5
LSB
-
Absolute accuracy
-
±2.0
±4.5
LSB
-
DNL differential nonlinearity error
-
±0.5
±1.5
LSB
-
INL integral nonlinearity error
-
±1.0
±2.5
LSB
-
High-precision
channels
(AN105, AN106)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.48
(0.267)*2
--
μs
Sampling in 16 states
Max. = 400 Ω
0.40
(0.183)*2
--
μs
Sampling in 11 states
VCC = AVCC0 = 3.0 to 3.6 V
3.0 V ≤ VREFH ≤ AVCC0
Offset error
-
±1.0
±2.5
LSB
-
Full-scale error
-
±1.0
±2.5
LSB
-
Absolute accuracy
-
±2.0
±4.5
LSB
-
DNL differential nonlinearity error
-
±0.5
±1.5
LSB
-
INL integral nonlinearity error
-
±1.0
±2.5
LSB
-
High-precision
channels
(AN107)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.75
(0.533)*2
--
μs
Sampling in 32 states
Offset error
-
±1.0
±2.5
LSB
-
Full-scale error
-
±1.0
±2.5
LSB
-
Absolute accuracy
-
±2.0
±4.5
LSB
-
DNL differential nonlinearity error
-
±0.5
±1.5
LSB
-
INL integral nonlinearity error
-
±1.0
±2.5
LSB
-
Normal-precision
channels
(AN116, AN117)
Conversion time*1
(Operation at
PCLKC = 60 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.88
(0.667)*2
--
μs
Sampling in 40 states
Offset error
-
±1.0
±5.5
LSB
-
Full-scale error
-
±1.0
±5.5
LSB
-
Absolute accuracy
-
±2.0
±7.5
LSB
-
DNL differential nonlinearity error
-
±0.5
±4.5
LSB
-
INL integral nonlinearity error
-
±1.0
±5.5
LSB
-
Table 2.34
A/D conversion characteristics for unit 1 (2 of 2)
Conditions: PCLKC = 1 to 60 MHz
Parameter
Min
Typ
Max
Unit
Test conditions



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