R5F5651EDDFM datasheet(156/188 Pages) RENESAS

156 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 156 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.16

GLCDC

Note 1. Parallel RGB888,666,565: Max. 27 MHz

Serial RGB888: Max. 30 MHz (4x speed)

Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All GLCDC AC timings are measured in combination with the pins in the same

group.

If we use group “-A” and “-B” combination, “LCD data output Delay timing (tDD)” is Min = –5.0 ns, Max = 5.5 ns.

Figure 2.79

LCD_EXTCLK Clock Input Timing

Figure 2.80

LCD_CLK Clock Output Timing

Table 2.44

GLCDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

LCD_EXTCLK input clock frequency

tEcyc

—

30*1

MHz

Figure 2.79

LCD_EXTCLK input clock low pulse width

tWL

0.45

—

0.55

tEcyc

LCD_EXTCLK input clock high pulse width

tWH

0.45

—

0.55

tEcyc

LCD_CLK output clock frequency

tLcyc

—

30*1

MHz

Figure 2.80

LCD_CLK output clock low pulse width

tLOL

0.4

—

0.6

tLcyc

LCD_CLK output clock high pulse width

tLOH

0.4

—

0.6

tLcyc

LCD_CLK output clock rise time

tLOR

——

LCD_CLK output clock fall time

tLOF

——

LCD data output delay timing

tDD

–3.5*2

—4*2

Figure 2.81

1/2 Vcc

VIH VIH

VIL

tDcyc, tEcyc

tWH

tWL

LCD_EXTCLK

tLcyc

tLOL

tLOH

tLOF

tLOR

LCD_CLK

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